Senior Design Verification Engineer | Upto $175/hr
Mercor is seeking a Senior Design Verification Engineer to work on AI model training for digital chip design and verification. The ideal candidate has 3-10 years of experience in digital RTL design or design verification, strong proficiency in Verilog/SystemVerilog and UVM, and a solid understanding of digital design fundamentals. Requirements 3–10 years of experience in digital RTL design or design verification Strong proficiency in Verilog/SystemVerilog and UVM Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols Experience with ASIC design flows and EDA tools Familiarity with leveraging LLM-based tools for chip design and verification workflows Benefits Generous Paid Time Off 401k Matching Retirement Plan Visa Sponsorship Four Day Work Week Generous Parental Leave Tuition Reimbursement Relocation Assistance Originally posted on Himalayas