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Mercor is seeking a Senior Design Verification Engineer to work on AI model training for digital chip design and verification. The ideal candidate has 3-10 years of experience in digital RTL design or design verification, strong proficiency in Verilog/SystemVerilog and UVM, and a solid understanding of digital design fundamentals. Requirements 3–10 years of experience in digital RTL design or design verification Strong proficiency in Verilog/SystemVerilog and UVM Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols Experience with ASIC design flows and EDA tools Familiarity with leveraging LLM-based tools for chip design and verification workflows Benefits Generous Paid Time Off 401k Matching Retirement Plan Visa Sponsorship Four Day Work Week Generous Parental Leave Tuition Reimbursement Relocation Assistance Originally posted on Himalayas
Engineering at Finalis Our engineering team is building the core infrastructure that powers private capital markets. As a Senior Software Engineer, youâll work closely with product managers, designers, and the leadership team to design and build high-impact products. Youâll be expected to thrive in a fast-paced, ambiguous environment, solve complex problems, and create ai-native technical solutions that deliver value to our customers and scale with our growth. The Role As a Sr. Software Engineer at Finalis, you will play a critical role in building and scaling our ai-native platform across our three core pillars: compliance, data, and payments. Youâll own significant parts of our system design and implementation, contribute to our technical roadmap, and mentor other engineers. This role requires strong technical expertise, the ability to navigate complexity, and a passion for creating reliable, secure, and elegant software. Responsibilities Design, build, and maintain scalable b